1. Technical Field
The present invention relates to a data transmission controller having a jitter reduction function and a sampling frequency converter using the data transmission controller. Specifically, the present invention relates to a sampling frequency converter appropriate for digital audio devices and the like.
2. Related Art
In the field of digital audio and the like, audio data is often interchanged between two devices that operate synchronously with each other, but based on respective independent clocks. In this case, a preceding device outputs data synchronously with the device's own clock. A subsequent device inputs data synchronously with the device's own clock. Generally, clocks of both devices contain jitters. To reduce jitters, a FIFO (First-In First-Out buffer) is inserted between both devices. Data is often transmitted via the FIFO. In addition to using the FIFO, PLL (Phase Locked Loop) control may be provided. The PLL control monitors the amount of data remaining in the FIFO such that a clock jitter may not cause the FIFO to overflow or underflow. When the amount of remaining data becomes greater than a appropriate value, the PLL control increases a data output speed in the FIFO, for example. When the amount of remaining data becomes smaller than a appropriate value, the PLL control decreases the data output speed in the FIFO, for example. In the field of digital audio and the like, there are provided devices that comply with various sampling frequencies. Devices with different sampling frequencies may be often connected to each other. In such case, a sampling frequency converter is used to adjust the sampling frequency of sample data output from a preceding device to the sampling frequency for a subsequent device. Japanese Patent Application Laid-Open Publication No. 11-55075 discloses the technology of applying the above-mentioned FIFO and PLL control to the sampling frequency converter.
The above-mentioned conventional technology increases or decreases the data output speed or the data input speed in the FIFO in accordance with a difference between the amount of data remaining in the FIFO and the appropriate value. When the speed is excessively increased or decreased in accordance with the difference, the amount of remaining data may vary with the time and data transmission operations may become unstable. That is, there is a time lag between adjusting a data output speed or the like and a resulting increase or decrease in the amount of remaining data. During the time lag, the data output speed or the like is still adjusted. When the amount of remaining data becomes stable, a variation in the amount of remaining data somewhat increases.
Digital audio devices and the like use various sampling frequencies such as 32 kHz, 44.1 kHz, and 48 kHz. There may be a case of connecting devices having different sampling frequencies to each other. When a receiving-side device operates at a fixed speed for reading data strings of an original signal waveform transmitted from a transmission-side device, an output signal waveform is distorted along the time axis. The original signal waveform is not correctly reproduced. To solve this problem, the transmission-side device may use a sampling frequency converter. This type of sampling frequency converter may have an interpolator. The sampling frequency converter accumulates a specified number of pieces of successively input past data. Each time the receiving-side device receives a data request signal having a given sampling frequency, the sampling frequency converter assumes that time point as an interpolating point. The sampling frequency converter generates data at this interpolating point by interpolating the accumulated data and supplies the generated data to the receiving-side device.
When data is supplied to the receiving-side device in the above-mentioned sampling frequency converter, the sampling point of that data corresponds to the timing to receive the data request signal. The data request signal needs to be so accurate as to contain no jitter. However, there is a limitation on removing jitters from the data request signal. A jitter inevitably occurs at the timing of the data request signal. An apparent jitter, when generated, disturbs equally spaced interval of data supplied from the sampling frequency converter to the receiving-side device. When the receiving-side device reproduces or records such data at a given time interval, the reproduced or recorded signal waveform is distorted from the original signal waveform represented by the data before conversion of the sampling frequency.